Variability and power aware clock network design in nanometer technologies
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Aggressive technology and clock frequency scaling have been key enablers to boosting integrated circuit (IC) performance over the past two decades. As technology scales further into the nanometer domain, maintaining the pace of frequency scaling in multi-GHz range has become difficult thus limiting performance enhancement that is expected. This can be attributed primarily to the impact of manufacturing variations and the dynamic temperature-voltage changes during run-time. These can cause unpredictable delay variations in the system that can result in functional failures and may limit the clock frequencies significantly. This situation is further exacerbated by the rising clock network power consumption. Robust clock design techniques often result in considerable power overhead, adding to the already large clock power. The primary goal of this dissertation is to develop design techniques that enhance robustness of clock networks against variations while ensuring minimum power consumption. In the first part of this dissertation, we examine the impact of variability on the clock distribution network (CDN). The impact of different sources of variations including random and systematic process variations, run-time temperature and supply voltage variations on CDN performance is analyzed through simulations in different technologies from 180nm to 45nm technologies. Simulation results show the rapidly growing impact of interconnect variability in sub-65nm technologies. It also identifies parts of the CDN that contribute significantly to the clock delay variations and clock skew. Using these results, we develop a new clock skew compensation technique with low area and power overhead to address interconnect variations. We apply this technique to the skew-sensitive parts of the CDN, identified earlier, thus maximizing its effectiveness. In the second part, we develop a clock tree buffer insertion methodology that optimizes the Clock network for power and robustness simultaneously. Towards this, we first model the delay variations in buffered global interconnects, which form the CDNs. This model is used to compute the maximum delay variation in the clock tree. We use this value as a metric to characterize the robustness of the clock tree, due to its simplicity and low computational cost. Also, through simulations, we show the effectiveness of the metric as compared to statistical clock skew, that is typically used. We present the optimal design methodology that ensures least power and area overheads in the clock tree while enhancing robustness, as measured by the new metric. These design techniques help reduce clock network safety margins with minimal performance penalties, resulting in low power consumption and higher clock frequencies. The CDN variability modeling and design optimization approaches developed can be extended to other parts of the system such as data path, memories and IO subsystems. We have illustrated the application of this work to designing robust global interconnects that play a key role in intra-chip communication between different IPs and logic blocks.