Power aware memory system design for Very Deep SubMicron (VDSM) SoCs
MetadataShow full item record
Modern embedded system applications assign a significant portion of chip area to embedded memories. Due to the rising memory-processor performance gap, these memories play a crucial role in determining system performance. As process technology scales into the 45 nanometer domain, the problem gets aggravated by additional factors such as deep submicron noise, increased sensitivity to Process, Voltage and Temperature variations (PVTs) and exploding leakage power consumption. While many circuit level techniques address these Very Deep Sub Micron (VDSM) memory design challenges, their impact may not be fully realized unless they are considered at the system level during the design process. In addition, with critical time-to-market requirements faced by chip design vendors, an early application oriented design exploration through modeling is important. This dissertation provides insights and guidelines towards developing speed, power, and process variation aware memory system design. In this research, we develop architectural choices for system level memory configuration based on benchmark programs. We also develop system level modeling technique that integrates low level cache circuit analytical models with system level access information to provide early design choices for leakage and process variation aware memory design. Through analysis, we establish that using multi-port memory in L1 cache that supports high Instructions Per Cycle (IPC), and multi-banked, multi-array configurations for large L2 caches, achieves leakage power savings. Our analysis on various memory and architectural solutions in terms of throughput and power consumption based on a set of benchmark applications provides architectural choices for reducing the memory performance gap. We develop a system level modeling tool, CacheLeakage, that integrates a high level processor simulator and circuit level cache analytical model. At the system level, we use processor simulator, SimpleScalar, to obtain cache access statistics through benchmark program runs. For the cache memory model, we use both conventional and alternative circuit styles of memory cell, array configuration and peripheral circuits to compute the physical parameters for each stage, and derive equations that predict the access time, the power (with emphasis on leakage) and process variation. We improved CacheLeakage tool, by incorporating compact models for intra-die V th and interconnect variations. The tool receives cache sizes, configurations (number of ports, line sizes, associativity), process technology information and leakage reduction techniques, and gives speed and power estimation for memory access. Combining speed and power estimation with the system level cache access information obtained through processor simulator, we have an overall assessment of access time/power of a given cache configuration used for an application processor, which also takes into consideration process variations. Such a tool can have a significant impact in SoC designs.