Escape routing studies in high input-output count area array packaging
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The input-output counts in electronic packages have significantly grown in number over the past few decades demanding advanced packaging technology. The number of I/Os is an important consideration in the physical design of integrated circuit packages and board level routing specially in advanced area array packaging which mainly comprises of flip chip technology at the die level and ball grid array packages at the electronic package level. The latest IC chips and their electronic packages have taken I/O counts to a very high level and this number will continue to increase in the coming generations of high performance electronic products. While both BGA and flip chip technology provides a good solution for high I/O count and high-density component packages, it also presents new challenges for substrate level routing since the number of substrate layers required for routing directly affects complexity, manufacturability and cost. This research addresses the fundamental problem of escape routing in area array packaging and presents novel and innovative approaches for I/O placement and escape routing. The main theme of this work is to determine the impact of I/O placement on the routability using a non-standard approach. This non-standard approach provides the flexibility to place I/O anywhere within the array to enhance its routability. A new routing method termed here as "balls shifted as needed method" has been developed and extended for routing in multiple layers. Continuous improvements have been demonstrated through the results. Intelligent design techniques have been presented to incrementally improve the overall results based on real world routing constraints. In addition, a new methodology of computer visualization has been applied to analyze the designs. To summarize this work presents advanced and innovative routing solutions to meet the current and future demands for Area Array Packaging and demonstrates area array routing as a multi-dimensional, multi-variable and multiple constrained problem. This essentially means that owing to increased complexity in the physical design the chip and the package cannot be designed independently of each other. The higher degree of interdependency between chip and package high level design has been demonstrated using an escape routing based co-design methodology. The physical routing design helps in developing an in-depth understanding of inter-dependency of routing design variable and constraints and utilizes novel methods for incremental improvements.