FPN reduction in logarithmic CMOS image sensors using floating gate circuits
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Logarithmic CMOS image sensors are extensively used in wide dynamic range imaging systems and as front ends for biologically inspired retinal computational systems. One of the main issues hampering their performance is the presence of Fixed Pattern Noise (FPN). Other issues limiting their performance are, poor response time at low light intensities and small output voltage swing. Recent techniques to overcome FPN require accurate reference signal generators and reduce the frame rate of the sensor array. In this work we attempt to overcome FPN by performing a one time, in-pixel calibration using floating gate circuits. We use the non-volatile and adaptive properties of floating gate transistors to remove FPN. We propose four novel pixel circuits that eliminate FPN and improve the output voltage swing. The test system consisting of a 30x39 pixel array along with their column calibration circuitry and 10 bit analog-to-digital converter (ADC) was fabricated in AMI 0.5 μm C5F process.