Multi-level power efficient and reliable VLSI circuits and systems – Tradeoffs
With continued scaling of CMOS technology, power efficiency and reliability are emerging as major challenges for the electronics and computing industry. This dissertation aims at exploring device, circuit, architecture, and application level solutions for developing power efficient and reliable VLSI Circuits and Systems. The developed methodologies and techniques are applicable to a wide range of applications in ultra-low-power mobile multimedia, high-performance computing with multi/many-core microprocessors, and application-driven design. First, we focus on power efficient SRAM for mobile multimedia applications. We have developed a low power SRAM design for MPEG-4 video processors. Considering both the process variation and aging effect, our design uses an optimal voltage for spatial voltage scaling, achieving strong power efficiency. In addition, by exploring the nature of the pixel data, we achieve a reliable operation at 0.36 V under process variation and NBTI aging effect. The developed memory achieves 95% reduction in power consumption, with no significant degradation in frame quality. We further investigate high level schemes for multimedia towards developing power efficient mobile systems. As a next step, we focus on power efficient circuit/architecture co-design for high-performance computing with multi/many-core microprocessors. We implement clock-delay-unit-combined local bit line (CB-LBL) to enable high read access speed and energy efficient operation for high performance register files, achieving 99.8% parametric yield. Also, we present a circuit-architecture co-design technique for power efficient and reliable tri-modal register files, by exploring register activity to improve the power efficiency. To meet design constraints of diverse applications, we develop four possible implementations that tradeoff power, speed, and design complexity, achieving greater design flexibility. Additionally, we develop an application-driven ALU design methodology to achieve a high level of power efficiency for modern microprocessors. Based on a PN-selection algorithm, our developed methodology enables designers to select power efficient dynamic modules for different applications. Finally, we focus on power efficient and reliable device/circuit co-design for modern processors. By exploring CMOS device's long-time reliability characteristics, we develop a hybrid-cell register files to achieve high reliability by storing the most vulnerable bits in robust 8T cells and other bits in conventional 6T cells. Based on 32 nm CMOS process, our design achieves 11.4% and 24.8% register file reliability improvement in high performance and embedded systems respectively, with negligible overhead. In addition, by analyzing the relationship between Process, Voltage & Temperature (PVT) variations, leakage characteristics, and sleep vectors in register files, we conduct a comprehensive study on sleep vector selection and develop guidelines to achieve low leakage and robust register files in modern processors.