Single-Ended Rail-to-Rail Low Power SAR ADC Design
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In this thesis, a novel dynamic comparator is proposed and implemented using the low power SAR ADC architecture. A bootstrapping technique is used within the sample-and-hold circuit to ensure simplicity and low power operation with a sufficient bandwidth. The dynamic latched-comparator reduces the power consumption and its PMOS and NMOS differential input pairs provide the rail-to-rail input range. The higher degree of dispersion from the binary-weighted capacitor array is used in the design to improve the mismatch error. The design was fabricated using the ON-Semi C5N process. It has a 3 metal layers and 2 poly layers, and a high resistance layer. The typical threshold voltages for NMOS and PMOS are 0.8 and -0.9, respectively. The process is optimized for 5 Volts mixed-signal application according to the foundry.