Efficient Architectures for High Speed Binary Multipliers
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Fast, efficient multiplication of binary operands in digital systems is a problem of critical importance to modern computing architectures. The efficiency of multiplier designs depends on the addition of partial products, and many methods of compressing partial products have been presented. These methods involve compressing bits of equal weight in iterative phases until two numbers remain to be added with a conventional adder circuit. In this work, advanced architectures for high speed, power, and area efficient binary multiplier circuits are presented for use with integer or fixed point operands. First, we present a full multiplier design called the Interlaced Partition Multiplier which is based on partitioning one input number into small groups of bits and interlacing every other partition with zeros. Each partition is multiplied by the other partitions and the presence of the interlaced zeros allows the partial products to be formed by concatenating the products of each partition without carries. Simulations show that multiplier can be built with this design that achieve new trade offs in terms of area and speed cost. Next, we present a novel bit stacking technique that can be used to implement binary counters for use in any multiplier topology. This counting technique can be used to build 6:3 and 7:3 Counters that outperform any other binary counter design and also consume less power. To demonstrate the effect of these fast, efficient counters, 64 by 64 bit Counter-Based Wallace Tree multipliers are implemented using existing binary counters and also the proposed counters. Simulations show that these full multiplier designs are faster and consume less power when built using the proposed counters. Thus, the proposed counters yield a pure gain when used to build multiplier circuits.