High Performance and Energy Efficiency in Network on Chip (NoC) Design
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With Moore`s law fading, presence of billions of transistors on a single chip, and diminishing performance from uniprocessor architectures, multicore chips are emerging as the prevailing architecture in both application-specific and general-purpose markets. As the core count increases, the need for a scalable on-chip communication fabric that can deliver high bandwidth continues to gain importance, leading recently to multicore chips interconnected with on-chip networks. Networks-on-Chip (NoC) is widely regarded as a promising approach for addressing communication challenges affiliated with Chip Multi-Processors (CMPs) in the face of further increases in integration density. However, throughput, energy efficiency and routing algorithms become more challenging in NoC design.