A 2-Step Noise Shaping Time-to-Digital Convereter
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In this work, a 2-Step Noise Shaping Time to Digital Converter is designed. This 2-step TDC attempts to combine classical TDC architectures with modern circuit techniques to overcome the limitations inherent to classical architectures. This TDC uses 2 step process with Flash TDC as coarse quantiser and a VCO as fine quantiser. This design aims to explore the improvements that can be brought to TDC designs with oversampling, and noise shaping. The Simulink model of this TDC achieves an SNDR of 53dB with ENOB of 8 bits. The circuits have been design in TSMC 65nm in Cadence Virtuoso and Simulink.