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dc.contributor.advisorSanyal, Arindam
dc.contributor.authorGupta, Ishita
dc.date.accessioned2019-07-30T15:11:48Z
dc.date.available2019-07-30T15:11:48Z
dc.date.issued2019
dc.date.submitted2019-05-17 00:02:21
dc.identifier.urihttp://hdl.handle.net/10477/80006
dc.descriptionM.S.
dc.description.abstractIn this thesis, a correlated double sampling assisted capacitance to digital converter is designed. The principle behind Correlated double sampling, assists the signal readout front end of the Capacitance to Digital converter, to be low power consuming. The CDS is based on sampling the input twice to ensure complete preservation of input differential swing. The front-end comprises of single stage Telescopic operational amplifier that provides high gain and phase margin. The readout front-end acts as an offset and gain calibrating stage with high noise suppression. This design aims at improving energy consumption of Capacitance to digital converters in comparison with conventional architectures. The proposed 10-bit SAR ADC is an energy efficient design that has Figure of Merit (FoM) of 73.43fJ/conversion-step. It consumes total energy of 0.0752nJ from a supply of 1.1V. The circuits are designed in TSMC 65nm technology.
dc.formatapplication/pdf
dc.language.isoen
dc.publisherState University of New York at Buffalo
dc.rightsUsers of works found in University at Buffalo Institutional Repository (UBIR) are responsible for identifying and contacting the copyright owner for permission to reuse. University at Buffalo Libraries do not manage rights for copyright-protected works and cannot assist with permissions.
dc.subjectElectrical engineering
dc.titleCorrelated Double Sampling Assisted Capacitance to Digital Converter
dc.typeThesis
dc.typeText
dc.rights.holderCopyright retained by author.
dc.contributor.departmentElectrical Engineering


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