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RIA: High-Performance VLSI Systems Using CMOS Wave- Pipelined Transmission Gate Logic
Wave pipelining eliminates the intermediate register stages in a pipelined system by using the internal capacitance of the combinational logic for temporary storage. to obtain a high operating speed, equal path delays must ...
Development of an Undergraduate VLSI Test Laboratory for Digital, Analog and Mixed-Signal Circuits
The purpose of this project is the development of an undergraduate VLSI laboratory for testing digital, analog, and mixed-signal circuits. The lab includes an integrated test platform based on a CMT Mixed-Signal Test Station ...